New capabilities provided by ADS 2006 Update 2 include:
Signal Integrity Verification Toolkit
Jitter Diagnosis including jitter type separation and BER/bathtub curves
Encrypted HSPICE Simulation
Other Important New Features
New Digital Signal Source for Signal Integrity Simulation - details
Built-In Signal Integrity Serial Link Serializer/Deserializer (SERDES) Components - details
EMDS Integrated 3D EM Simulation - EMDS for ADS - details
64-bit Ptolemy Simulation on Windows platforms - details
System C Co-simulation - details
Faster phase noise modeling when using the AVM Automatic Verification Model
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Jitter Diagnosis including jitter type separation and BER/bathtub curves
For data rates 5 Gbps and above jitter analysis is important when optimizing serial data link performance, and also provides a tool to quickly and accurately predict link BER (Bit Error Rate) performance. Accurate jitter analysis of a serial link helps designers identify the components in a serial link that contribute the highest amount of jitter so they can be addressed and corrected. The earlier in the design cycle such jitter issues are highlighted, the more successful will be the initial design iterations resulting in fewer costly PC board "spins." The designer can now accurately predict a link's jitter budget specification as a direct function of BER performance.
Jitter Analysis in ADS 2006 Update 2 could be used to decompose the aggregate total jitter of serial data into its individual jitter components such as random jitter (RJ) and deterministic jitter (DJ) at the receiver. The ADS jitter analysis leverages the techniques utilized in the Agilent DCA-J equivalent-time sampling and Infiniium DSO80000 real-time oscilloscopes. This method exploits smart extrapolation to predict low BER performance utilizing an efficient minimal-length bit pattern simulation. In ADS 2006 Update 2, the extrapolated BER values are obtained from the Dual-Dirac model of the jitter statistics. Jitter Analysis and Encrypted HSPICE are both part of the Signal Integrity Verification Toolkit.
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Encrypted HSPICE
This feature has been designed specifically for the high-speed, serial-link Signal Integrity designer whose primary design platform is ADS. These designers typically develop transmitter and receiver models and need to perform a final verification step using vendor-supplied encrypted HSPICE models.
The encrypted HSPICE simulation flow utilizes four main steps:
Importing Encrypted HSPICE.
Creating Your Design.
Simulating the Design.
Evaluating Results.
Importing an encrypted HSPICE subcircuit points to the encrypted HSPICE netlist fragment. A typical import provides ADS with a representation of all of the files; the external files are no longer needed. However, with the encrypted HSPICE flow, a placeholder is constructed that points to the actual file so that the location of the file can later be passed to the HSPICE simulator.
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New Digital Signal Source for Signal Integrity Simulation
The Pseudo-Random Bit Sequence source (PRBSsrc) is capable of generating waveforms distorted along amplitude and time axes, to represent realistic binary signals at an arbitrary point in a digital communication system.
Digital sequences may be supplied to the PRBSsrc in one of five possible data modes:
Maximal Length LFSR RegisterLength
Maximal length pseudo-random sequence for an x-bit register is 2x -1 bits long. The Taps and Seed settings are automatically generated within the source for any value of register length between 2 and 32 bits.
User Defined LFSR
Taps and Seed to create a PRBS bit sequence.
Explicit Bit Sequence
An arbitrary number of bits may be specified by manually editing the bit string. Internally up to 232 -1 bits are supported before the bit sequence is repeated.
Bit File
Supports reading from an ASCII file to create a bit sequence. The advantage of this mode is that it can support custom encoding and scrambling schemes.
External Trigger
The EdgeShape capability allows the selection of standard analytical functions for defining the waveform during transitions between any two voltage levels.
Supported edge shapes are:
Linear transition.
Raised Cosine transition.
Error Function transition.
Rise and fall times can be supplied in various formats, such as:
0 -100%
10 - 90%
20 - 80%
30 - 70%
De-emphasis capability of this digital source allows pre-distortion of a signal as a function of bit width and amplitude. DeEmphasisMode can be set to Percent Reduction or to dB Loss, both signifying a decrease in the steady-state or shelf dynamic range relative to peak dynamic range.
PRBSsrc supports two classes of jitter, both of which are independent of the data content produced by the source, namely Random Jitter and Periodic Jitter.
Random Jitter is defined as timing disturbances that occur as the result of device noise and flicker effects in the transmission hardware. It is defined as a unimodal Gaussian distribution with a mean of zero and standard deviation of RJrms along the time axis.
Periodic Jitter is defined as the timing disturbance that occurs as a result of Electro-Magnetic Interference (EMI) from switching on and off of power supplies. It results in deviation of the bit transition boundary in a periodic fashion where the amplitude of the variation occurs along the time axis and is denoted by PJamp. The frequency of variation, which is unrelated to the BitRate of the digital signal, is denoted by PJfreq.
Three variations of periodic waveforms are supported in contemporary jitter injection:
Sinusoid
Square
Triangle
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Built-In Signal Integrity Serial Link Serializer/Deserializer (SERDES) Components
Time-dispersive channels can cause intersymbol interference (ISI). For example, in a dispersive channel, the receiver sees delayed versions of a symbol transmission, which can interfere with other symbol transmissions. An equalizer attempts to mitigate ISI and thus improve the receiver's performance. Various equalization schemes could be utilized to correct for FFE depending upon the distraction in a signal. Feed forward (FFE) and decision feed back (DFE) equalization schemes are most commonly used for 6 to 10 Gbps applications.
ADS 2006 Update 2 provide new equalizer components such as Feedforward Equalizer, Decision Feedback Equalizer, Blind Decision feedforward Equalizer, Blind Decision Feedback Equalizer, encoders and decoders.
The FFE and DFE utilizes provides various choices for tap optimization such as:
Least Mean Square (LMS)
Zero Forcing (ZF)
Recursive Least Square (RLS)
The blind FFE and DFE provides the following tap optimization algorithms:
Constant Modulus Algorithm (CMA)
Decision Direct (DD)
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EMDS Integrated 3D EM Simulation - EMDS for ADS
Electromagnetic Design System (EMDS) for Advanced Design System (ADS) is a complete solution for electromagnetic simulation of arbitrarily-shaped, passive three-dimensional structures.
EMDS for ADS makes full 3D Finite Element Method (FEM) EM simulation an attractive option for designers working with RF circuits, MMICs, PC boards, modules, and Signal Integrity applications.
It provides the best price/performance 3D EM simulator available, with a full 3D electromagnetic field solver, and fully automated meshing and convergence capabilities for modeling arbitrary 3D shapes such as bond wires, vias and finite dielectric substrates (dielectric bricks).
EMDS in now integrated into ADS as "EMDS for ADS." Along with the Momentum planar EM simulator, it provides RF, Signal Integrity, and microwave engineers access to some of the most comprehensive EM simulation tools in the industry. EMDS for ADS users need very little background in electromagnetic field theory in order to operate and achieve accurate, meaningful solutions.
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64-bit Ptolemy Simulation on Windows platforms
The ADS Ptolemy software provides the simulation tools you need to evaluate and design modern communication systems products. Today's designs call for implementing DSP algorithms in an increasing number of portions in the total communications system path, from baseband processing to adaptive equalizers and phase-locked loops in the RF chain. Cosimulation with ADS RF and analog simulators can be performed from the same schematic.
Using the ADS Ptolemy simulator you can:
Find the best design topology using state-of-the-art technology with more than 500 behavioral DSP and communication systems models.
Co-simulate with RF and analog simulators.
Integrate intellectual property from previous designs.
Reduce the time-to-market for your products.
ADS Ptolemy also features:
Timed synchronous dataflow simulation.
Easy-to-use interface for adding and sharing custom models.
Interface to test instruments.
True mixed signal simulation is the strength and unique capability of ADS since it came to an existence. Ptolemy simulator along with Analog and EM simulation provides the capability to simulate the entire high speed serial link consisting of analog, DSP, and physical components.
ADS 2006 Update 2 can now utilize the power of 64 bit architecture on the Windows platform.
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SystemC Co-simulation
ADS SystemC co-simulation enables you to simulate your Signal Processing SystemC design in the same schematic with other ADS Ptolemy components. This integrated capability provides complete design flexibility complementing other ADS modules and co-simulations, including:
HDL co-simulation
MATLAB co-simulation
Co-simulation with Analog/RF Systems
The ability to design all portions of a communications product in one integrated environment can eliminate design errors resulting from disconnects among design teams. By co-simulating with SystemC designs, you can easily incorporate your existing SystemC intellectual property into new designs.
With SystemC co-simulation, you can test baseband designs in SystemC with extensively tested and robust ADS RF Models. Furthermore, SystemC co-simulation with Ptolemy DSP Models, HDL, and MATLAB enables you to validate your design at different level of design abstraction. This co-simulation capability in one design environment makes it easy to test SystemC design along with complex ADS system designs and see the effect on the entire system.
It is possible to co-simulate multiple instances of SystemC in ADS Ptolemy. This includes several instances of the same SystemC executable or instances of different SystemC executables. Designs in SystemC can be multirate. In multirate designs, inputs/outputs can consume/produce more than one data point during a single simulation run of a model. The SystemC co-simulation provides support for such SystemC models to be co-simulated in ADS.
The next version is 2006 Update 3,and then 2008.
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